The present invention relates to frequency synthesizers and more specifically, to frequency synthesizers which produce an output frequency higher than the input frequency.
In digital communications systems, it is often necessary to provide a clock signal with a frequency different from that of the available reference signal. This necessity may require independent crystal oscillators if both frequency sources need to be spectrally pure. However, independent crystal oscillators increase the cost of the equipment and can cause problems if the crystal oscillators drift differently with age and temperature.
One approach to solving the above problem of different required frequencies is to synthesize a signal with a high frequency from a reference signal having a reference frequency.
Using well known phase locked loop (PLL) techniques, this high frequency is generated and is then divided into a lower desired frequency. Typically, the reference frequency is multiplied by an integer factor N to produce the high frequency and then divided by another integer factor M to obtain the desired frequency. This method works well if the desired frequency is a convenient ratio of the reference frequency such as 1/2, 3/2, or 5/6. However, if the desired frequency is not a convenient ratio of the reference frequency, this method can prove cumbersome. For example, if the desired frequency is 12 MHz and the reference frequency is 19.68 MHz, the reference frequency must be multiplied by N=25 and the resulting frequency must be divided by M=41. The very high frequency generated in this example would result in higher power consumption for integrated circuits.
An alternative approach is to divide the reference frequency and then multiply the divided frequency to obtain the desired frequency. However, this method has a significant drawback in that phase noise is multiplied along with the divided frequency.
U.S. Pat. No. 3,976,945 provides yet another alternative. This patent discloses performing a non integer division of the input signal to obtain an output signal with the desired frequency. However, in this case the output frequency must necessarily be less than the input frequency. If the desired frequency were higher than the input frequency, this method would not be applicable.
Accordingly, there is a need for a method and an apparatus which can provide a desired output frequency higher than the input frequency without the power consumption and phase noise of the above methods.
The present invention provides a method and apparatus which provides a signal with an output frequency higher than an input frequency. A phase generator generates multiple phase signals from the input signal with each phase signal having the same frequency as the input signal but being out of phase with the input signal by multiples of a set time interval. These phase signals are transmitted to a multiplexer. The multiplexer output is determined by a select word generated by an accumulator from a stored value. The accumulator is clocked by the multiplexer output and the accumulator adds a control word with a set value to the stored value in the accumulator. This addition is accomplished at every cycle of the multiplexer output. By judiciously choosing control word and the time interval between phases, frequencies higher that the input frequency can be generated at the multiplexer output.
In a first aspect, the present invention sees to provide a frequency synthesizer for producing an output signal based on an input signal and a predetermined control signal, the input signal having an input frequency, the output signal having an output frequency higher than the input frequency, the synthesizer comprising: a multiphase reference generator having means for generating a plurality of phase signals from the input signal, each phase signal having a frequency substantially equal to the input frequency, and each phase signal being out of phase with the other phase signals by a multiple of a predetermined time interval; a multiplexer having means for receiving the plurality of phase signals, and having means for selecting one of the plurality of phase signals as a multiplexer output signal; and a phase selector having means for receiving the predetermined control signal and the multiplexer output signal, and having means for generating a phase selector output signal based on the control signal and the multiplexer output signal; wherein the phase selector output signal is operatively coupled to the means for selecting one of the plurality of phase signals, and the multiplexer output signal is the frequency synthesizer output signal.
In a second aspect, the present invention seeks to provide a frequency synthesizer for producing an output signal from an input signal based on a predetermined control signal, the input signal having an input frequency, the output signal having an output frequency higher than the input frequency, the synthesizer comprising: a multiphase reference generator having means for generating a plurality of phase signals from the input signal, each phase signal having a frequency substantially equal to the input frequency, and each phase signal being out of phase with the other phase signals by a multiple of a predetermined time interval;
a multiplexer having means for receiving the plurality of phase signals, having means for selecting at least two of the plurality of phase signals, and having means for blending/interpolating the at least two of the plurality of phase signals into a multiplexer output signal; and a phase selector having means for receiving the predetermined control signal and the multiplexer output signal, and having means for generating a phase selector output signal based on the control signal and the multiplexer output signal; wherein the phase selector output signal is operatively coupled to the means for selecting one of the plurality of phase signals, and the frequency synthesizer output signal is the multiplexer output signal.
In a third aspect, the present invention seeks to provide a frequency synthesizer comprising: a phase generator having means for receiving an input signal having a reference frequency and means for generating a plurality of phase signals having a frequency substantially equal to the reference frequency, each phase signal being out of phase with the input signal by a multiple of a predetermined time interval; a multiplexer having means for receiving the plurality of phase signals, and having means for selecting one of the plurality of phase signals as a multiplexer output signal, a binary digital accumulator having a clock input, an accumulator input and an accumulator output, the multiplexer output signal being operatively coupled to the clock input; and a storage means for storing a predetermined control word, the storage means being operatively connected to accumulator input, wherein the predetermined control word is added by the binary digit accumulator to a stored value on every cycle of the multiples output the multiplexer output is selected by the selector output and is based on at least one of the plurality of phase signals and each successive multiplexer output leads its predecessor by a multiple of the predetermined time interval.
In a fourth aspect, the present invention seeks to provide a method of synthesizing an output signal from based on an input signal and a predetermined control signal, the input signal having an input frequency, the output signal having an output frequency higher than the input frequency, the method comprising the steps of:
(a) generating a plurality of phase signals from the input signal;
(b) selecting one of the plurality of phase signals as a selected phase signal;
(c) generating the output signal from the selected phase signal;
(d) adding the predetermined control word to a stored value to generate a select signal based on the selected phase signal;
(e) selecting one of the plurality of phase signals as the selected phase signal based on at least a portion of the select signal;
(f) repeating steps (c) to (e) for every cycle of the output signal.